Example embodiments relate to sense amplifier circuits and semiconductor memory devices. More particularly, example embodiments relate to sense amplifier circuits in semiconductor memory devices having open bit line structures and the semiconductor memory devices.
As an integration degree of a semiconductor memory device has increased, a cell size has been decreased, and bit line loading has been increased.
An open bit line structure may be used to reduce the bit line loading. In the open bit line structure, a sense amplifier circuit is disposed between a pair of adjacent memory cell sub-arrays in a memory cell array, and a voltage difference between a bit line of the left memory cell sub-array and a bit line of the right memory cell sub-array is sensed by the sense amplifier circuit. Accordingly, compared with sensing a voltage difference between adjacent bit lines of the same memory cell sub-array, the open bit line structure may minimize the loading effect between the bit lines.
However, in the open bit line structure, half of the memory cells in the leftmost or rightmost memory cell sub-array are not used, which results in the increase of the chip size. Thus, the leftmost and rightmost memory cell sub-arrays may be replaced with balance capacitors. However, even if the balance capacitors are designed to have the same loading as the bit line of the memory cell sub-array, it may be impractical for the balance capacitors to have the same distribution.
In equalizing a pair of bit lines during a bit line pre-charge operation, the optimal target pre-charge level of the bit line pair may be VA/2, where VA is a bit line operating voltage or a bit line power supply voltage. However, if there is a loading mismatch between the bit lines, the voltage of the bit lines may not reach the optimal target pre-charge level, or VA/2. In this case, a charge sharing voltage between the bit lines may be reduced, which results in a sensing failure.